Key details about AMD’s Zen based Naples CPU have surfaced online, allowing awaiting enthusiasts a sneak peek into what to expect from the chip giant’s forthcoming feature-rich chip for the HPC market.
The new details show that AMD is planning on an optimized GPU server platform with Naples. It will feature a maximum of 128 PCI Express Gen 3.0 lanes. The reason behind including such a sheer high number of lanes is to offer support for a vast amount of devices.
As you will see in the block diagram below, Naples come with a 1U rack that can support up to 32 NVMe devices, as well as four discrete GPUs. It will also feature a couple of InfiniBand EDR interconnects to facilitate a smooth data flow between server and storage systems.
AMD calls this 1U rack “Maximize Compute Density”, hinting that we are probably looking at the denser Naples config with 32 cores and 64 threads. Note that the 2U rack is called “Maximize Performance/Node” and it provides a heightened level of GPU support, facilitating up to 26 NVMe devices, 6 discrete graphics cards, as well as a single IB EDR link.
AMD has outlined some of the key benefits of using 1U and 2U racks. These include 4 – 6 directly connected discrete GPUs. Also, the Radeon Technologies Group currently seems to be working to deliver Vega-based products roughly around the same time as Naples so at least some of them can be coupled with Naples processors. Any such interconnect will ensure a smoother P2P communication channel between the GPUs in addition to doing away with the need to have PCIe 3.0 switch (resulting in low latency and optimal bandwidth between CPU and GPU).
Finally, the Zen based high-end Naples platform will bring support for a massive 8-channel memory to ensure that they can take mass datasets for use cases such as rendering, molecular dynamics, data analytics, and graphics. Better still, both 1U and 2U racks will feature support for:
- 1U (2 x CPU, 4 x GPU)
- 2U (2 x CPU, 8 x GPU)
- Sled: 2P (multi-CPU, 1-2 x GPU)
- Blade: 2P (multi-CPU, 1-3 x GPU)
AMD Naples specs
|L1 Instruction Cache||32 KB x 32|
|L1 Data Cache||64 KB x 32|
|L2 Cache||512 KB x 32|
|L3 Cache||64 MB|